1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device and a semiconductor system including the same for performing a repair operation on a memory cell.
2. Description of the Related Art
In general, as the capacity of a semiconductor system increase, the reliability and yield of the semiconductor system may deteriorate. Thus, the semiconductor system improves the reliability and yield thereof by adding an error correcting code (ECC) to data and repairing an error of a defective memory cell.
FIG. 1 is a block diagram illustrating an ECC circuit of a typical semiconductor memory device. Referring to FIG. 1, the typical semiconductor memory device includes a memory cell array 100, a data put/output unit 140 and an ECC circuit 120.
The memory cell array 100 stores input data DATA and outputs data DATA, which is stored on the memory cell array 100.
The data input/output unit 140 receives the input data DATA, which is provided from an external device (not shown), and transmits the input data DATA to the memory cell array 100. The data input/output unit 140 outputs data DATA, which is outputted from the memory cell array 100, to the external device.
The ECC circuit 120 determines whether an error occurs in data DATA stored on the memory cell array 100, and corrects the error when the data DATA is outputted from the memory cell array 100 to the external device. The ECC circuit 120 also determines whether an error occurs in input data DATA, which is inputted to the memory cell array 100, and corrects the error. Thus, the reliability of the data DATA, which is inputted or outputted to/from the semiconductor memory device, may be improved.
However, since the ECC circuit 120 is added to the semiconductor memory device, an area of the semiconductor memory device increases. Moreover, since an operation of the ECC circuit is performed on the data, which is inputted or outputted to/from the memory cell array 100, if an error occurs in the data, it may be difficult to synchronize the data with an operation clock after the error is repaired.